1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to transistors having strained channel regions by using stress-inducing sources, such as stressed sidewall spacers of gate electrodes, embedded strain-inducing semiconductors alloys and the like, to enhance charge carrier mobility in the channel region of a MOS transistor.
2. Description of the Related Art
Generally, a plurality of process technologies are currently practiced to fabricate integrated circuits, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode located close to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region is a dominant factor determining the performance of MOS transistors.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith, such as reduced controllability of the channel, also referred to as short channel effects, and the like, that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. For instance, the thickness of the gate insulation layer, typically an oxide-based dielectric, has to be reduced with reducing the gate length, wherein a reduced thickness may result in increased leakage currents, thereby posing limitations for oxide-based gate insulation layers at approximately 1-2 nm. Thus, the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques, for example, for compensating for short channel effects, with oxide-based gate dielectric scaling being pushed to the limits with respect to tolerable leakage currents. It has, therefore, been proposed to also enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby offering the potential of achieving a performance improvement that is comparable with the advance to a future technology node while avoiding or at least postponing many of the problems encountered with the process adaptations associated with device scaling.
One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance, by creating tensile or compressive stress in the vicinity of the channel region to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, creating uniaxial tensile strain in the channel region along the channel length direction for a standard crystallographic orientation increases the mobility of electrons, which in turn may directly translate into a corresponding increase in the conductivity. On the other hand, uniaxial compressive strain in the channel region for the same configuration as above may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach for further device generations, since, for example, strained silicon may be considered as a “new” type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.
For this purpose, a plurality of mechanisms have been developed that may be appropriate for creating a desired high strain component in the channel region of transistor elements. For example, dielectric materials, such as silicon nitride, silicon dioxide and the like, may be deposited with a high internal stress level which may be taken advantage of to provide a specific type of strain in the adjacent channel region. Silicon nitride is a frequently used material for forming sidewall spacer elements on sidewalls of gate electrode structures and may be deposited with tensile or compressive stress, which may then be transferred into the channel region via the gate electrode structure. In other approaches, the isolation structures that usually delineate respective active regions of transistor elements may be provided in the form of shallow trench isolations in sophisticated applications, wherein silicon dioxide, silicon nitride and the like may be used as insulating fill materials, which may also be provided in the form of a compressively stressed material, thereby exerting the corresponding stress on the transistor active region, which may finally result in a corresponding strain component in the channel region. In still other approaches, a strain-inducing semiconductor material may be locally incorporated or embedded in the transistor active regions, for instance in the drain and source areas, thereby also creating a corresponding strain in the adjacent channel region.
Moreover, after completing the basic transistor structure, additional strain-inducing mechanisms may be applied, for instance, by providing highly stressed dielectric materials above the transistor structure, for instance in the form of an etch stop material that may typically be used during the patterning of an interlayer dielectric material that is provided for passivating the circuit elements and providing a platform for forming additional wiring levels of the semiconductor device. Thus, transistor performance may be efficiently enhanced on the basis of one or more of the above-identified strain-inducing mechanisms, wherein, however, the finally achieved gain in performance may be less than expected due to a significant “absorption” of stress, which may be caused by the presence of the gate electrode structure. That is, it is assumed that the material of the gate electrode may act as a significant barrier with respect to the stress transfer mechanism, for instance provided by stressed spacer elements, embedded strain-inducing semiconductor material, stress-inducing isolation structures and the like. Since even a moderate increase of transistor performance may be associated with significant efforts with respect to the adaptation or new development of complex manufacturing techniques, as previously described, it is highly desirable to more efficiently exploit any mechanism for enhancing transistor performance, such as any of the above-described strain-inducing mechanisms.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.